1. Field of the Invention
The present invention relates to a logic module, and more particularly, to a programmable logic module and upgrade method thereof.
2. Description of the Related Art
Programmable logic devices such as FPGAs have wide applicability due to their flexibility and reprogrammability. An FPGA typically includes an array of configurable logic blocks (CLBs) connected across a configurable routing structure for implementing desired logic functions and circuit design. Thus, the FPGA occupies a larger area on the wafer surface. FPGAs also include a number of configuration memory cells coupled to the CLBs to specify the function to be performed by each CLB, and a number of configuration memory cells coupled to the configurable routing structure to specify the connectivity between CLBs.
FPGAs are most commonly used within systems including a microprocessor and a memory unit. As shown in FIG. 1, an available FPGA 120 receives a configuration bitstream from memory device 100 upon receipt of a program signal from microprocessor 110, to erase previous configuration data and receive new configuration data from memory device 100. Thus, the FPGA 120 can implement new logic functions and circuit designs according to new configuration data.
FIG. 2 shows a conventional FPGA module. The FPGA module has a circuit board with a FPGA 18, a downloading unit 12, and a memory device 16 disposed thereon. The memory device 16 is plugged into a socket 14 on the circuit board 10. The configuration data stored in the memory device 16 is written into the FPGA by the downloading unit 12. When FPGA gate count is increased and the desired functions and circuits are more complex, a memory device with a larger storage capacity is required. The conventional memory device 16, however, is formed within a dual-in-line package (DIP), the maximum storage capacity of which is only 8 Mb. Thus, DIP memory 16 in the conventional FPGA module limits the upgrade capacity of the FPGA 18.
FIG. 3 shows another conventional FPGA module. This FPGA module has a circuit board 30 with an FPGA 38 disposed thereon, a downloading unit 32, and a plurality of memory devices 36. The memory devices 36 are plugged into the circuit board 30 through the corresponding sockets 34. Configuration data stored in the serial memory devices 36 is written into the FPGA 38 by the downloading unit 32. As shown in FIG. 3, the circuit board 30 has eight memory sockets 34 to receive the memory devices 36. Typically, serial memory devices have slow write speed, and are expensive. Additional, when FPGA gate count is increased and the desired functions and circuits are more complex, a memory device with a larger storage capacity is required. A new circuit board with more sockets is necessary when the eight serial memory devices cannot sufficient to store the desired configuration data. Thus, the FPGA 38 of the conventional FPGA module has limited the upgrade capacity.
Further, the FPGAs 18 and 38 shown in FIGS. 2 and 3 both have a plurality of I/O terminals and power terminals, each of the I/O terminals and power terminals is connected to a corresponding pin (20 or 40) on the circuit board 10 and 30. Insertion force between the pins (20 and 40) of the FPGA and the corresponding connector (not shown), however, increases with increased pin count. Thus, it is inconvenient to insert or remove the FPGA from the connector.